The present application relates to semiconductor technology. More particularly, the present application relates to interconnect structures which contain an intermetallic compound (i.e., metal alloy), as a cap and/or a liner, that is formed by reacting an interconnect metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. The present application also relates to methods of forming such interconnect structures.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structures typically include copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size decreases, the practical significance of EM increases.
EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductors of interconnect structures due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnect structures varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the interconnect, which eventually results in a circuit dead opening.
It has been demonstrated that by replacing the Cu/dielectric interface with a Cu/metal interface can enhance electromigration resistance by greater than 100 times. Prior art metal caps such as CoWP require that a high quality interface be present between the Cu interconnect region and the metal cap. The need of a high quality interface between the Cu interconnect region and the metal cap reduces the process window for forming interconnect structures. As such, a need exists to provide methods that widen the process window for fabricating interconnect structures having high electromigration resistance.